( ESNUG 577 Item 3 ) ---------------------------------------------- [10/27/17]
Subject: One user's quickie eval of Real Intent AutoFormal and Ascent Lint
REALINTENT ASCENT LINT vs. ATRENTA SPYGLASS LINT
Over the same week, I also tried the Ascent Lint tool. Used it
two designs. First design was 850K gate with 3 asynchronous clocks.
Second design was 4 million gates and 5 async clocks.
Immediately, I ran into a problem with Ascent Lint crashing on
our Verilog code. Real Intent R&D quickly identified the lint rule that was
causing the crash and delivered a new version that worked correctly. We
were surprised to see a hard crash but I was glad to get a quick fix to our
problem in under 24 hours.
Both the Atrenta and Real Intent lint tools don't need any setup other than
picking which rulesets to run on the design. By default we ran the entire
set of Ascent Lint rules on our Verilog and SystemVerilog source code. The
runtimes were faster to what we had seen with Meridian CDC and Ascent XV.
On the 850K gate design the runtime was ~1 minute and for the 4 million gate
design it was ~5 minutes. That's 5.8 K gates to 13.3 K gates per sec!
Besides the runtime, I liked the format of the report file, and the minimal
report "noise" with very few false positives with Ascent Lint. Ascent's
source code debug with the SNPS Verdi interface was able to visualize each coding
issue easily.
Despite the initial crash, Ascent Lint worked well with good performance.
- from "Why we switched from Atrenta to Real Intent for RTL lint"
From: [ Super Commando Dhruva ]
Hi, John,
Please keep me anonymous.
I was browsing DeepChip and found this 2016 user comment about Ascent Lint.
Thought I'd follow up with my own 2017 Ascent Lint story.
That earlier user was designing SoCs. We do IP and we're targeting for it
to fit onto the 28nm Xilinx Kintex 7.
The IP we're developing is a 10GbE MAC written in 200,000 lines of Verilog
RTL. We use Cadence Incisive to simulate. Our 10GbE MAC IP core handles
the flow of data between a client and Ethernet network through a 10-Gbps
Ethernet PHY. On the transmit path, the MAC accepts client frames and
constructs Ethernet frames and forwards them to the PHY. Similarly, on
the receive path, the MAC accepts Ethernet frames via a PHY, performs
checks, and removes the relevant fields and forwards frames to the client.
Full-duplex mode is supported where our IP core does transmission and
reception handled simultaneously.
It operates on 3 different clock domains. For the 28nm Xilinx Kintex 7,
the maximum frequency is 327 MHz and occupies 3960 LUTs and 3019 FFs.
OUR ASCENT LINT EXPERIENCES
Using Ascent Lint, ee caught few important issues in our design. One of
our FSMs was missing a default statement. The designer missed this issue
because it was slightly involved because of the pragmas and `defines in our
Verilog RTL source code. The tool quickly found this issue and we made the
RTL fix for this. (There were few other minor FSM related issues it found
which we passed on to the design team to resolve.)
What we found evaluating Ascent Lint:
- From the start we noticed that Ascent Lint is very easy to run inside
the Cadence Incisive environment. Within minutes of tool getting
installed we were able to run it on our IP with practically no time
spent on setting up the tool.
- We like the incremental report generation because it identifies any
additional issues when we create newer version of RTL.
- Integration with Synopsys Verdi for signal tracing and code browsing.
- We also liked the lint rules in Ascent Lint that checks the use of
the Synopsys full-case parallel case pragmas. (John, as you know,
these pragmas can also change the functionality of a design causing
a mismatch between pre-synthesis and post-synthesis simulation --
which if not discovered during gate-level simulations will cause an
ASIC to be taped out with design problems.)
- We did not make a point-to-point comparison with Spyglass, but found
Ascent-Lint is comparatively easy to work with.
- Better signal-to-noise ratio for Ascent Lint. Other lint tools like
SpyGlass and Leda, have reported issues which were not actually
design problems; Ascent Lint does this much less so.
After the end of our evaluation, we have decided to use Ascent Lint on our
next IP development project. We also recommend Ascent Lint to our IP
clients as a cheaper alternative to Spyglass.
OUR ASCENT AUOTFORMAL EXPERIENCES
As a side test, we also did an eval of their Ascent AutoFormal on our same
200,000 lines of Verilog RTL for our 10GbE MAC IP.
We did not have the man-power to do full Formal with something like Jasper,
but we wanted as least some Formal testing out our IP functionality.
BACKGROUND: While running RTL simulation, any test failure has one of three
possible causes. It could be due to:
- a testbench bug, or
- the verification engineer did not write the test correctly,
- or there is a real functional bug in the RTL.
Every time a test fails, it takes a lot of time and effort for our engineers
to find the exact source of the problem. AutoFormal helped us pinpoint RTL
code problems without a testbench. Which in turn saved our debug time.
- Overall Ascent AutoFormal helped find a few corner case bugs that
we missed in simulation. Nothing big, but it felt good to have
them found.
- It improved our code coverage. We used to spend considerable amount
of time trying to figure out how to create the right stimulus so that
all lines of code was be executed. Sometimes there are blocks of
code that cannot be reached due to an RTL bug; or we're spending lot
of time and simulation cycles trying to figure out how to create the
"right" stimulus to execute a block of code that cannot be reached
due to a RTL bug.
AutoFormal helped us find these blocks of dead code without any
testbench. Using the built-in automatic assertions in AutoFormal,
we were able to fix bugs at the early stage of our design phase to
get 100% code coverage.
- Like their linter, AutoFormal generated a report with very little
noise. We liked their smart reporting structure which groups errors
as Primary or Secondary. If the designer fixes a failure in the
Primary category, usually a large number of errors in the Secondary
category will automatically disappear. This allowed us to focus on
the few primary issues for our design and also significantly reduced
the amount of noise within the report.
- The tool also handles duplicate Verilog modules correctly. Our design
had 5 instantiations of the same module. AutoFormal reported 1
problem in the FAIL section of the report. The other 4 failures were
reported in a category called DUPLICATE. Upon fixing the bug in the
FAIL category, the 4 failures in the DUPLCATE category disappeared;
again reducing the amount of noise within the report.
- Like Ascent Lint, their AutoFormal is integrated with the Synopysy
Verdi debugging platform for code browsing and signal tracing.
We also bought AutoFormal and recommend it to our IP clients.
- [ Super Commando Dhruva ]
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